On chip embedded memory with non-volatility can enable energy and computational efficiency. However, leading embedded memory options such as Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) suffer from high voltage and high current-density problems during the programming (i.e., writing) of a bit-cell.
For example, large write current (e.g., greater than 100 μA) and voltage (e.g., greater than 0.7V) may be required for tunnel junction based Magnetic Tunnel Junction (MTJ) to perform a write operation in a MTJ based STT-MRAM bit-cell because write operation may require writing through tunnel oxides. Another problem with STT based bit-cells is that they suffer from reliability issues due to high tunneling current in MTJs. Also, the energy barrier (i.e., kT, where ‘k’ is the Boltzmann's constant, and ‘T’ is temperature) to overcome during switching is a fixed quantity leading to several unfavorable design tradeoffs.
For example, for fast STT based bit-cells, lower kT is desired. However, lowing kT may require more refresh operations on the STT bit-cells. Likewise, a higher kT improves magnet memory retention in STT bit-cell. However, higher kT slows the operations of STT based bit-cells.